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nonideal Transistor - Coggle Diagram
nonideal Transistor
Designer
Threshold drops
pMOS pull down |Vt|
nMOS pull up Vdd-Vt
Leakage Current
subthreshold
Vt-Vgs decrease leakage
low Vt -> high performance
high vt -> low leakage
leakage current critical -> need feedback
Vdd
Vel-Sat -> no USE
Vdd should be decrease
delay
series deliever 1.5배 current
pMOS < nMOS
High Field Effect ->Ids decrease than expected
Velocity saturation
High Vds roll off velocity
Ec
Mobility Degration
High Vg decrease Ids by u
Vel sat I-V effect
Ids increase with Vdd
a model
parameter variation
Speed
tox : thin
Leff : short
Vt : low
Enviromental Variation
Process Corner
Temperature Sensitivity
temp decrease Ion
Temp increase Ioff
channel Length modulation
Ids increase with Vds in sat!
Threshold Voltage effect
Vt 바뀐다
Body effect
Vsb increase Vt
Drain Voltage
Vds decrease Vt
tunneling
short channel effectS
drain source dep 영역 -> shorten channel length
leakage
off current
subthreshold leakage
on off 아닌상태
high Vt good
gate leakage
oxide 얇아서 tunneling
Diode leakage
p-n 접합은 전류가 센다
Drain induced Barrier lowering
Vds increase leakage
(-) gate Voltage
