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Circuits and Layout - Coggle Diagram
Circuits and Layout
Pass transistors
Signal Strength
NMOS PASS 0
PMOS PASS 1
Transmission Gates
Tristates
Tristate Inverter
EN = 1 -> 통과
MUX
Y = (D0)
(S)' + (D1)
(S)
Transmission Gates
bubble은 0에 어울린다.
Inverting Mux
inverter 2개
CMOS Latches & FF
D Latch
1일 때 Transparent
0일 때 기억
Flip Flop
Latch의 Sampling time 줄인다.
Race Condition
CMOS Gate Design
Inverted Input A' -> A
Complement
STD Celll
Diffusion Cap
P-N접합
Stick Digram
