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DRAM ECC - Coggle Diagram
DRAM ECC
No Work
SSC disable
Driving strength raising
2019 synopsys flow
CKE patch
Raise VDT10 core power threshold from 0.8 to 0.86
Next Step
Check register value of DRAM
Review flow.
Synopsys help??
PS4 resume
DRAM read/write error
code is gone
LoadISP fail
DRAM tain/ RW test pass
possible reason
core power
Timing
init flow
Reproduce
Intel RDT test script
Intel IPC platform
question
POR don't fail for DRAM read/write?
CorePower ready time is different.
Why to see different pattern?