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ADEC (Digital propagation/contamination delay (counter (MOD number…
ADEC
Digital
propagation/contamination delay
information processing
sampling
Nyquist Theorem on sampling frequency
quantization
Shannon: log2(1/pk) bits
encoding information
redundancy
boolean algebra
sum of product
K-map
De Morgan's Law
logic gate
AND, OR, XOR, NOT, NAND, NOR, XNOR
counter
ripple counter
parallel counter
MOD number
counter with MOD < 2^n
CLR of JK FF
pre-settable counter
PRE of JK FF
memory
latch
+CLK
S-R latch (set/reset)
D latch (data)
flip-flop
S-R FF
SR latch + CLK
D FF
D latch + CLK
J-K FF
#
SR FF + Q feedback
CLK
Positive/Negative Going Transition (PGT/NGT)
Finite State Machine
#
Filters
bandpass
bandreject
high pass
low pass
Analog
time domain response
differential equation
natural response
impulse response
step response (DC input)
first order RC/RL circuit
time constant
step
impulse
second order RLC circuit
over/critically/under damped
frequency domain response
Laplace transform
partial fraction expansion
bode plot
first order system
cutoff frequency
1/Time Constant
2nd order system
centre frequency
cutoff frequency x2
beta
Q factor
Q = 1/(2*Damping Ratio)
Two-port Networks
parameters
a
z
h
g
y
interconnection
#
cascading
series
seris-parallel
parallel
parallel-series