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DigitalDesign (Register (Shift Registers (Shift Register w/ Parallel Load,…

- - - - Shift = 0
        
        Load = 0
        
        No change
        
        Load = 1
        
        Load parallel data
      - Shift = 1
        
        Shift down from Q0 to Q3
      - Di = Shift' & Load' & Qi + Shift' & Load & Ii + Shift & Qi-1
      - D-ff
    - - D-ff
    - - Serial adder
        
        D-ff
        
        input
        
        y = shift reg B
        
        z = D-ff state
        
        x = shift reg A
        
        output
        
        FA
        
        s >> store in reg A
        
        c >> store in D-ff
        
        CLK = clock & shift control
        
        JK-ff
        
        Excitation table
        
        State table
        
        Jq & Kq & S equation
      - Serial Transfer
        
        2 shift registers
        
        CLK = clock & shift control
    - - MUX + D-ff
  - - - D inputs
        
        Load = 0, Di = Qi
        
        Load = 1, Di = Ii
    - - C inputs
        
        Load = 0, C inputs = 1
        
        Load = 1, C inputs = Clock
        
        clock gating
- - - - count-up
        
        negative-edge triggered D-ff
        
        without 1 input
        
        T-ff
      - count-down
        
        Approach 1
        
        Modify count-up's CLK input
        
        Approach 2
        
        positive-edge triggered D f-fs
    - - Accumulation of propagation delay
    - - State diagram
        
        Count sequence
      - J-K ff
      - Q1
        
        C1 = clock
        
        J1 = 1
        K1 = 1
        
        Q2
        
        C2 = Q1(down)
        
        Analyze
        
        Q8 = 0 >> Q2'
        Q8 = 1 >> reset
        
        J2 = Q8'
        K2 = 1
        
        Q4
        
        C4 = Q2(down)
        
        J4 = 1
        K4 = 1
        
        Q8
        
        C8 = Q1(down)
        
        Analyze
        
        Q4 & Q2 = 0 >> reset
        Q4 & Q2 = 1 >> Q8'
        
        J8 = Q4 & Q2
        K8 = 1
      - Three-decade BCD counter
        
        9 -> 10
        
        Q8 : 1 >> 0
        
        negative-edge
        
        push next digit
  - - - Count-Up
        
        D-ff
        
        Present state & next state & output
        
        JK-ff
        
        EN = 0
        
        Ji = 0
        Ki = 0
        
        EN = 1
        
        J1 = 1
        K1 = 1
        
        J2 = A0
        K2 = A0
        
        J3 = A0 & A1
        K3 = A0 & A1
        
        1 more item...
        
        T-ff
        
        EN = 0
        
        T0 = 0
        
        EN = 1
        
        T0 = 1
        
        T1 = A0
        
        T2 = A0 & A1
        
        1 more item...
      - Up-Down
        
        T-ff
        
        Up = 1
        
        up-counting
        
        T0 = 1
        
        T1 = A0
        
        1 more item...
        
        Up = 0 & Down = 1
        
        down-counting
        
        T0 = 1
        
        T1 = A0'
        
        1 more item...
        
        Up = 0 & Down = 0
        
        no-counting
        
        T0 = Up + Up' & Down
        
        T1 = Up & A0 + Up' & Down & A0'
        
        T2 = Up & A0 & A1 + Up' & Down & A0' & A1'
    - - State diagram
        
        State table (excitation table)
    - - Clear
      - CLK
      - Load
      - Count
  - - - Binary counter + decoder
        
        n-bit binary counter + an n-to-2n-line decoder
      - Ring Counter
        
        a shift register (ring-counter) w/ 2n flip-flops
      - Johnson Counter
        
        k-bit switch-tail ring counter >> 2k distinguishable states
        
        其他
        
        1 0 相鄰對應的bit
        
        全部 1 和全部 0 的
        
        找 A 和 E
- - - - programmable read-only memory
    - - programmable array logic
    - - programmable logic array