Please enable JavaScript.
Coggle requires JavaScript to display documents.
:earth_asia: [ RISC-V ] :desktop_computer: Online_Study_Group since 2018…
:earth_asia: [ RISC-V ]
:desktop_computer: Online_Study_Group
since 2018
Resource
:notebook_with_decorative_cover:
Web-Site
:spider_web:
Great Ideas in Computer Architecture (Machine Structures)
:star:
CS61C Fall 2017
CS61C Spring 2015
CS61C Spring 2018
:star:
CS61C Fall 2018 :star:
CS61C Spring 2019
:explode:
CS 61A: Structure and Interpretation of Computer Programs
CS61C Spring 2018 :star:
SCALA
18-447 Introduction to Computer Architecture, Spring 2018
CS152 Computer Architecture and Engineering
CS252 Graduate Computer Architecture
riscv-soc-cores :star:
:star:
6.175: Constructive Computer Architecture (Fall 2017)
: :star:
CSE 564: Computer Architecture, Summer 2017
:star:
FPGA
ALTERA
DE1-SoC Board
:star:
qSoC, or how to build an FPGA SoC from scratch
:star:
:star:
VexRiscv
:star:
#
A FPGA friendly 32 bit RISC-V CPU implementation
DE1-SoC-MTL
:star:
Scala
Functional Programming Principles in Scala
Coursera's Functional Programming Principles in Scala Course Materials :star:
Functional Program Design in Scala
Parallel programming
Object-Orientation, Abstraction, and Data Structures Using Scala
:star:
Scala
ONLINE RESOURCES
SCALA TUTORIAL
A SCALA TUTORIAL FOR JAVA PROGRAMMERS
Scala Tutorial
ProceedingsArchive
:star:
1st RISC-V Workshop Proceedings
7th RISC-V Workshop Proceedings
:star:
RISC-V Workshop in Chennai Proceedings
JULY 19, 2018
Inaugural RISC-V Summit Proceedings, Dec. 3-6, 2018 :explode:
HW
SiFive Documentation
Untethered lowRISC tutorial
A guide to the development environment
CS 250: VLSI Systems Design
Spring 2017
seldridge/rocket-rocc-examples
VHDL
:star:
HDLBits — Verilog Practice
:star:
PULP Platform
:explode:
github
bigPULP
RISC-V manycore accelerator for HERO, bigPULP hardware platform
SystemVerilog
RI5CY: RISC-V Core
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
SystemVerilog
CSEE 4840 .Embedded System Design Spring 2019
CSEE 4840 .Embedded System Design Spring 2014
youtube
Wed1315 - PULPino A small single core RISC-V SoC - Andreas Traber, ETH Zurich
doc
Low Power Floating-Point Unit for RISC-V
PULP Project Update
RISC-V Tutorial
Spring 2018 :: CSE 502 — Computer Architecture
GitHub
:cloud:
RISC-V
JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.
RISC-V Assembly Programmer's Manual-manual
:star:
RISC-V ELF psABI specification
riscv-qemu
RISC-V Toolchain Conventions
riscv/meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architecture
riscv/riscv-tools
:star:
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
gnu-mcu-eclipse
:star:
:star:
freechipsproject
rocket-chip
:star:
Rocket Chip Generator
riscv/riscv-pk
RISC-V Proxy Kernel and Boot Loader
Chisel 3
:star:
chisel
:star:
Constructing Hardware in a Scala Embedded Language
riscv-sodor :explode:
Educational microarchitectures for risc-v isa
Chisel 3 wiki
:star:
Builtin Operators
Width Inference
Instantiating Modules
Short Users Guide to Chisel
:star:
Chisel Tutorials (Release branch)
Chisel Tutorials (Release branch)
:star:
리눅스 커널 소스 및 RISC-V 아키텍쳐 분석 공유
:star:
seldridge/rocket-rocc-examples
Video Lecture
:computer:
UC Berkeley CS 61C Great Ideas in Computer Architecture (Machine Structures)
#
Spring 2015 -- Computer Architecture Lectures -- Carnegie Mellon
RISC-V Workshop Barcelona May 7th 2018
:star:
Design of Digital Circuits - ETH Zürich - Spring 2018
Computer Architecture - ETH Zürich - Fall 2017
DE1-SoC lectures 2017
:star:
Introduction to FPGA Design for Embedded Systems
:star:
FPGA computing systems: Background knowledge and introductory materials
:star:
Computer Organization and Design (RISC-V)
:star:
risc v berkeley hardware for your berkeley software
Computer Architecture - ETH Zürich - Fall 2018
Paper :newspaper:
carrv.github.io
:star:
Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018)
:star:
First Workshop on Computer Architecture Research with RISC-V (CARRV 2017)
:star:
Krste Asanović, Publications by Year
Papers with regards to RISC-V in Google Scholar search results
arxiv.org
:star:
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes
Program Synthesis Through Reinforcement Learning Guided Tree Search
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices
TextBook :books:
Computer Organization and Design RISC-V edition
:star:
Table of Contents :thinking_face:
1 Computer Abstractions and Technology
2 Instructions: Language of the Computer
3 Arithmetic for Computers
4 The RISC-V Processor
:pencil2:
5 Large and Fast: Exploiting Memory Hierarchy
6 Parallel Processors from Client to Cloud
Appendix
B Graphics and Computing GPUs
C Mapping Control to Hardware
D A Survey of RISC Architectures
A The Basics of Logic Design
Errata
RISC-V Reference Data (Green Card)
Lecture Slides
컴퓨터 구조 및 설계 - 하드웨어 / 소프트웨어 인터페이스(MIPS), 5th Edition :warning: :!:
Computer Organization and Design, Enhanced, 5th Edition
Advanced Content and Appendices
Glossary
Index
Further Reading
MIPS Reference Data (Green Card)
Computer Organization and Design RISC-V Edition 5/E
교보문고_(판매가 : 48,000원) :star:
Computer Architecture.A Quantitative Approach, 6th Edition
:star:
Table of Contents
:thinking_face:
Fundamentals of Quantitative Design and Analysis
Memory Hierarchy Design
Instruction-Level Parallelism and Its Exploitation
Data-Level Parallelism in Vector, SIMD, and GPU Architectures
Multiprocessors and Thread-Level Parallelism
The Warehouse-Scale Computer
Domain Specific Architectures
A. Instruction Set Principles
B. Review of Memory Hierarchy
C. Pipelining: Basic and Intermediate Concepts
Lecture Slides
:star:
Errata (updated 28 Nov 2017)
:star:
Scala
Learning Scala
LearningScalaMaterials
Article & Etc.
:rolled_up_newspaper:
RISC-V Poster Preview - RISC-V Foundation
Igniting the Open Hardware Ecosystem with RISC-V - FOSDEM 2018
RISC-V Instruction Set Manual
:star:
Volume I: User-Level ISA
Official
:star:
Volume I: User-Level ISA
:star:
Document Version 2.2
Draft
Volume I: User-Level ISA
:star:
Document Version 2.3-draft
Volume II: Privileged Architecture
Official
:star:
Volume II: Privileged Architecture
Privileged Architecture Version 1.10
Draft
Volume II: Privileged Architecture
Document Version 1.11-draft
Why we need RISC-V
C++ links: RISC-V Assembly
:star: :
C++ links: computer architecture
:star:
Leveraging RISC-V for AI and Machine Learning
Software Tools
:star:
How to install the RISC-V toolchain?
: :star:
Information :information_desk_person:
Time
:alarm_clock:
매주 토요일 13:30 ~ 16:30 (UTC+09:00)
Objectives:red_flag:
컴퓨터 아키텍쳐 리뷰 (Computer Organization and Design RISC-V Edition_ The Hardware Software Interface)
:check:
RISC-V 스펙 리뷰, 개발 환경 이해
:check:
향후 논의 하여 Target Core 및 SoC 선정; 분석 및 구현
:check:
향후 논의 하여 주제 선정
:check:
스터디후기
YouTube
Privileged ISA
LMARV-1
:star:
LMARV-1
LMARV-1: A RISC-V processor you can see. Part 1: 32-bit registers.
Building a CPU on an FPGA
:star:
Building a CPU on an FPGA, part 1
https://www.youtube.com/watch?v=2fNBkUCjhcE&list=PLEeZWGE3PwbZ44SUf1-vA-UuX9_J_pifB
Wed1315 - PULPino A small single core RISC-V SoC - Andreas Traber, ETH Zurich
RISC-V "Rocket Chip" SoC Generator in Chisel - 1st RISC-V Workshop
:explode:
Chisel Quick Tutorial - 1st RISC-V Bootcamp
:explode:
[ RISC-V ]
Online_Study_Group_2019
Topic :fountain_pen:
pulp :explode:
SystemVerilog
CSEE 4840 .Embedded System Design Spring 2019
CSEE 4840 .Embedded System Design Spring 2014
Modelsim:question:
Target :question:
Rocket RISC-V
chisel
:star:
riscv-sodor :explode:
Educational microarchitectures for risc-v isa
Constructing Hardware in a Scala Embedded Language
Time
:alarm_clock:
Objectives:red_flag:
Resource
:notebook_with_decorative_cover:
RISC-V Cores and SoC Overview
:explode:
BOOM: Berkeley Out-of-Order Machine
Rocket Chip Generator
riscv-mini
The Potato Processor
RI5CY: RISC-V Core
VexRiscv
A FPGA friendly 32 bit RISC-V CPU Implementation