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Vector Architecture (Multiple Lanes (image (for(int i = 0; i< size;…

- - - - Instead of waiting for the first iterationto finish before we move on we split up the work
        
        The first iteration won't depend on the second or third so we can handle them at the same time
- - - - Fixed length bank which holds a single vector
        
        VMIPS has 8 registers
        
        Each register holds 64 elements, each element is 64 bits wide
    - - Also fully pipelined
        
        Handles the loads and stores for vectors
        
        Also normally handles the scalar loads and stores
        
        Summary:
        
        The vector load/store is always working but from time to time will communicate with the scalar load/store for help
        
        While this happens the functional unit will make sure everything is functioning by handiling and managing hazards
        
        1 more item...
    - - Each unit is fully pipelined
        
        A new operation can start on every clock cycle
        
        Used to detect hazards on register access
        
        There are 5 for the VMIPS strucure we're looking at.
        Handles 3 Floating Point,Integer, and Logical hazards
    - - Can provide data as inpuut to vector functional units
        
        Can also compute addresses to pass to vector load/store unit