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Discrete Time Transceiver Bibliography summary (Common Issues (EXAMPLES,…
Discrete Time
Transceiver
Bibliography summary
Common Issues
Switched Capacitors
Discrete Time
Filters
N-path Filters
FelipeKalinskiFerreira
Tunable High-Q N-Path Band-Pass Filters:
Modeling and Verification
Good introduction to N-path filters
Bring the
comportamental
expalation of the behavior of the system,
a VERY GOOD ONE, in time or freq. domain
\( f_{s} \) controls the \( f_{c} \) and C controls the band
Analysis of the transfer function, and state space analysis
Clock signal must be less than \( \frac{1}{N} \)
Development of a RLC equivalent model
Noise Modeling
Increasing switch size, improve linearity and \( r_{ON} \)
Implementation of a 4-path diff filter (65nm)
Power consuption (2 to 16) mW
Voltage gain = -2dB
Q = 3 to 29
IIP3 = 14dBm
NF = 3~5 dB
Charge Sharing
Filters
FelipeKalinskiFerreira
Analysis and Design of I/Q Charge-Sharing
Band-Pass-Filter for Superheterodyne Receivers
A brief comparission between N-path and CS filters
CS-BPF does not generate IM2 products
A very didatic explanation of a DT IIR filter
Explain the complex transfer function
for freq. below \( \frac{f_s}{10} \) the CS-BPF can
be modeled by a continous time model (RC)
Heterodyne architecture probably have the IF freq.
bellow \( \frac{f_s}{10} \), so, its a good model
25% of duty-cycle provides better conversio gain
and introduce less flicker noise.
Justify the IF selection by the flicker noise corner
Provides a excellent mismatch robustness
Implementation Issues implement a notch response arround
DC, so this topology is recommended for \( i_f \geqslant 30MHz \)
EXAMPLES
LateX commands for math
\( \int_{-\infty}^{x} e^{\frac{-(t-\mu)^2}{2 \sigma^2}} \mathrm{d}t \)
\( \begin{pmatrix} 1 & 0 \\ 0 & 1 \\ \end{pmatrix} \)
Lists
UM
DOIS
.....
ONE
TWO
....
Nested 1
Nested of nested1
Nested of nested of nested 1
Nested 2
Task List
Item 1
Item 2
Item 3
citing someone
FelipeKalinskiFerreira
HAHA!
GuilhermeCavalheiro(guilgec)
PBNSilva
Formatting References
Transmitter (TX)
DAC
C-2C
PA
ARQUITECTURES
FelipeKalinskiFerreira
BLE TX with ADPLL, a class E-F PA and a 36% efficiency - Bogdan Stawzewski
-Switched mode VCO
ADPLL
GFSK modulation scheme
Receiver (RX)
Frequency Synthetizer (SX)
ARCHITECTURES
barbarasouza
Function-Reuse Class-F DCO-PA and
an ADPLL
the VCO normally operates at the double of the
transmitting frequency, to reduce the injection pulling of the VCO when the PA starts-up. That's consume a lot of power.
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