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Fetch Execute Cycle (The Fetch Execute Cycle describes the basic steps a…
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- The program counter copies the address of the next instruction it contains into the Memory Address Register (MAR)
- The MAR places the address register to be used on to the 'address bus'
- The MAR triggers a 'read' signal that causes main memory (RAM) to place the instruction being asked for on to the 'data bus'
- The instruction on the data bus is landed into the data register (also called memory buffer register)
- The MDR copies the instruction into the 'instruction register'
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MEMORY DATA REGISTER (MDR)- temporarily Stores data being fetched from or written to the main memory of the CPU
Instruction Address Register (IAR)- It temporarily stores the current instruction to be decided the executed having been fetched from main memory
Arithmetic Logic Unit (ALU)- This is vital and it is the end of the fetch-execute cycle. The ALU will carry out the logical part of the instruction for example a calculation