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Fetch - Decode - Execute (Fetch (The fetch operation is responsible for…
Fetch - Decode - Execute
The Cycle
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First there is a fetch operation, then a decode operation and then an execute operation. Then another fetch begins and the cycle starts all over again.
The software to be run is located in main memory. Then the operating system loads it, ready for the CPU to use. The very first instruction in the program needs to be loaded into the CPU (fetch).
The fetch action loads an instruction into the CPU then the decode and execute stage take place inside the CPU. Once the first cycle is complete, the CPU fetches the next instruction.
Fetch
The fetch operation is responsible for getting an instruction or data from main memory into the CPU.
Programs do not necessarily start at location zero. Start with a program that begins at location [e.g.] 305 in main memory.
At the start of fetch, the program counter (in the CPU) is pointing to location 305 in RAM. As this is a new program assume that the accumulator is set to zero. [If the program had already been running for a while the accumulator would most likely contain a different value.]
Step 1)
- Program Counter: 305
- MAR:
- MDR:
- Instruction Reg:
- Accumulator: 0
Step 2)
The PC value gets copied into the MAR
- Program Counter: 305
- MAR: 305
- MDR:
- Instruction Reg:
- Accumulator: 0
Step 3)
Once the MAR is loaded, the Control Unit loads the address (305) on to the address bus and also sends a signal to main memory to read the instruction contained at that address.
- Main Memory Address: Location 305
- Content: ADD #5
- [location 305 in RAM contains an instruction 'add #5'].
Step 4)
The instruction ADD #5 is copied into the MDR
- Program Counter: 305
- MAR: 305
- MDR: ADD #5
- Instruction Reg:
- Accumulator: 0
Step 5)
Then the instruction in the MDR is copied into the Instruction Register so that it is ready to use during the next stage (decode) and Step 6) one location is added to the program counter
- Program Counter: 306
- MAR: 305
- MDR: ADD #5
- Instruction Reg: ADD #5
- Accumulator: 0
Registers
Registers used are:
- The MDR
- The MAR
- Program Counter
- Accumulator
- Instruction Register
Decode
In the 'decode' stage, the control unit reads the Instruction Register (Add #5) and makes sure that it is an instruction that the CPU can carry out i.e. it is in its instruction set. If it is, then various parts of the CPU are prepared for the next stage (execute).
Execute
The final stage is 'execute' which just means carrying out the instruction that has been decoded. In this case, the instruction is to add 5 to the value in the accumulator.
- Program Counter: 306
- MAR: 305
- MDR: ADD #5
- Instruction Reg: ADD #5
- Accumulator: 5