2017 Self Assessment Objectives (Support EE FPGA Activities (Supervise…
2017 Self Assessment Objectives
Hunter --FPGA and Fieldbus R&D
Plan XP content of Hunter CM Xilinx FPGA
Support Synergy Build Management for Hunter FPGAs
Researched various Fieldbusses and presented results and possible topologies. Considered CAN, MODBUS, EtherCAT and Spacewire primarily.
SFC MGR FPGA Verif.
Completed the UVM verification environment for the SFC MGR FPGA which was comprised of multiple DP . Finished writing predictors and scoreboards for the interfaces I was responsible for and integrated them with the interfaces that Wayne was working on. Managed to run basic test sequences on all the FPGA interfaces. SFC project was cancelled prior to this work but we used this this environment to demonstrate how to design an easily reusable and adaptable UVM environment for any CPU2K style FPGA. We learned useful information that can be applied to future projects.
Learned about the ARM family and various peripherals and interfaces.
Researched Embedded PCs
Performed Processor AOA with the HW and SW team members.
Looked into ARM SOCs from various vendors. Met with Jeff Halio and eventually settled on NXP or Xilinx offerings.
Determined the best eval. board options from Xilinx and NXP and had these vendors come in to present the tool flow involved in creating a design.
Had WC document the QVIP/UVMF/Python workflow for use by the group. Useful for when Jimmy starts verification activites.
Explained my vision for cross functional training in the Digital group so that each member is proficient in both design and simulation of XPs and FPGAs
Had JV and WC go to UVM Training class.
Had WC learn the QSYS build process for both Personality and CPU3K FPGAs by working with Bob Dumas on the Hunter BSM designs.
Altera FPGA Obsolescence
Analyzed the clocking schemes for each of the FPGAs being converted by the sustaining group. Noted poor design practice of array driven clocks. Educated the group on the correct way to divide down clocks an keep them synchronous using MMCM blocks in Xilinx. and how this is essential to achieve timing closure..
Taught the group how to set up timing constraints an achieve timing closure. Taught them about multicycle and false path and how to prevent analysis between unrelated time domains.
Found several latches in the TUV FPGA design. Educated the group about how latches are bad and should be avoided. Redesigned 2 modules to eliminate the latches and distributed the code as an example to the group that can be used for future reference.
Ran AutoCheck tool on each of the designs to try to uncover additional problems.
Support EE FPGA Activities
Performed AXI Rewite of PWM XP, Buzzer XP and Motor XP (3)
Supervise and Plan AXI DP (XP) feasibility, conversion and benchmarking
Had JV Develop AXI Host and Client Bridges.
Had JV put AXI bridges in CPU3K Altera FPGA
Aided JV with Hardware debug and simulation of XP
Had Mentor train the group and enable use of Questa VIP for AXI4 Lite. Had them demonstrate how to use QVIP Configurator with UVM Framework methodology.
Have WC do UVM Verif. of Client Bridge XP
Created AXI DP Benchmarking Scenarios for JV to perform on both Xilinx Pers and CPU3K FPGA. Use Arty Board
Learn AXI4 Protocol.
Created UVMF/QVIP AXI4 Verification environment tfor the BUZZER_XP I designed. Simulated the design.and corrected some AXI4 error reporting issues that were discovered.
Support FPGA Build Management for Infinity
Cataloged all DP and Verification status. Created prioritized road map for AXI conversion. Priority given to Pers. FPGA and number of designs utilizing a particular XP
Bifrost FPGA redesign for Y-Cable switchbox
New PDA FPGA work. Create DIRs and SAP Release PDA FPGAs for or both Cyclone and ACEX FPGA.
Researched BitBucket as a replacement for Synergy revision control. Learned how to use the tool and discussed the baselining flow for DP and linking DP to FPGAs
Evaluated the Mentor AutoCheck tool that uses formal verif. methods to detect Hdl design issues. Had BT put this tool into the SW mix.