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FPGA Physical Synthesis (Routing (May require multiple iterations…
FPGA Physical Synthesis
Placement
Goals
Wire-length
Routeablility
Timing
Algorithms
Analytical
Linear Objective Function - minimize mean
Quadratic Objective Function - minimize std. dev.
Difficult to add in new constraints
Minimum Cut
Simulation/heuristics
Simulated Annealing
See notes for implementation
Evolution
See notes for implementation
Force-Directed
Easier to add in new constraints
Constructive
Iterative Improvement
Routing
Routing Resource Graph (directed)
Nodes represent physical points to be connected
Short and Long Wire segments
Logic Block Pins
Edges represent potential connections
Wire Connection Block cont. prog. connection switches
Routing Switch Block cont. prog. routing switches
Maze Routing Algorithm
Grid Graph
May require multiple iterations
Rip up and reroute some invalid routes
Change cost of using certain nodes
Pathfinder congestion-delay algorithm
criticality (see formula in notes)
Cost (see formula in notes)