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DSPs Digital Signal Processors (Data Address Generators (DAGs) (Modify…
DSPs
Digital Signal Processors
OVERVIEW
Are single chip Microprocessors optimised for Digital Signal Processing
Carry out certain functions quicker than other micros
Take analogic values from the real world and (after they have been converted via A/D) manipulate them.
ADSP - 2100 family
Example of DSP processor
Architecture
Arithmetic Logic Unit (ALU)
Multiplier/accumulator
Barrell Shifter
All above can process 16 bit data
Data Address Generator (2 off)
Program sequencer
Modified Hardvard architecture
Memory
Data memory
Stores data only
Program memory
Stores instructions
Stored data as well
4 memory buses connected to external memory
Cached Memory
can store 16 words
Used to store next instruction in case we want PMD and DMD to be used to fetch data at the same time (quicker)
If the code uses a loop of up to 16 words, PMD and DMD can be used ONLY to fetch data for the duration of the cycle
Buses
PMA: Program Memory Address
Carries the "next instruction Address". It calls the next address to be looked up
14 bits wide
can address up to 16k lines of data (2^14 = 16,384)
PMD: Program Memory Data
Transfers instructions from the address indicated by PMA to internal instruction register (e.g. Program instruction register, ALU or M ultiplier input registers)
24 bits wide
DMA: Data Memory Addres
24 bits wide
Direct addressing: address comes directly from the instruction code
Indirect addressing: Address comes from output of Data Address Generator
PM buses support only direct addressing
Indicates address where data should be stored
DMD: Data Memory Data
16 bits wide
Transfers content of registers into any other register or external memory in one cycle.
Content is stored in the register indicated by DMA address
R: Result
Interconnects computetional units
i.e. Allows to process ALU results in Multiplier
PMD-DMD bus exchange
Allows data to be transferred from one bus to the other
Direct transfer of data from compuitational unit registers
Is provided with suitable hardware to overcome bit width discrepancy (16 - 24)
Data Address Generators (DAGs)
DAG 1
Supplies addresses to DMA
DAG2
Supplies addresses to DMA & PMA
They generate addresses that the program can use rather than using absolute addresses directly.
By working in pairs they allow for "dual-operands" instructions to be performed.
This reduces overhead (time and steps necessary to carry out an instruction)
Index register (I)
Contains the memory address and acts as a pointer
e.g. AX0=DM(I8,0)
This instructs DAG2 to write data to address listed in I8 to AX0 without modifing it (0)
I0...I7: DAG1
I8...I15: DAG2
Modify register (M)
Is the step size the value in the index needs to be incremented by
In this form: AX0=DM(I8,M8)
AX0 is given the value of I8 as it is
At next cycle I8 is modified by the increment in M8 and AX0 updated with new modified value (POST MODIFY)
i.e. I8 = 10 and M8 = 1, I8 becomes 11
M0...M7: DAG1
M8...M15: DAG2
In this form: AX0=DM(M8,I8)
AX0 is given the value of I8 already modified by M8
PRE MODIFY
Length register (L)
L0...L7: DAG1
L8...L15: DAG2
Base register (B)
B0...B7: DAG1
B8...B15: DAG2