Well, regarding R and C corners:
On small designs with short wires, the C of wires is more significant, so CMAX extraction is the worst case for setup.
On big design with long wires, the R of wires may became more significant, so RMAX is important.
Even in one hierarchical design, you may use CMAX for sub-blocks STA and RMAX for top-level STA (for example).
Note, that true RCMAX is impossible, because if wire is wider, than typical, the R is lesser and C is bigger, and vise versa (honestly, there is such corner as RCMAX, but it means that common RC influence on timing is worse here). Which combinations of R and C gives the worst timing for the current design can not be predicted, you should try all of this corners to find the worst one.
Regarding PVT corners, here you need take into account such effect as temperature inversion (it may happens or not, depends on library, depends on list of gates in your design ...). Another point, STA with IR-drop annotated to each gate in your netlist - Ptime requires for such kind of STA at least two libraries with the same process and temperature, but with different voltage.