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PG074 - Aurora 64B/66B (General Information (Tranceivers (Supported (GTX
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Block Diagram Figure 2-1
Performance
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Data transfer
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Frames
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the clock compensation blocks must be
transmitted for at least three cycles every 10,000 cycles
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Clock Interface - Figure 3-1
Clock Setup
- Set the gt_ref_clock to the Aurora IP
- Aurora IP outputs tx_out_clk
- Add tx_out_clk to the BUFG
- Add the BUFG to user_clk, txusr_clk, txusr_clk2 ...
- Feed the IP back with the txusr_clk
- Use the user_clk to drive the data to the IP
Clocks
phase-locked
- sync_clk
- user_clk
- tx_out_clk
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Reset Logic
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Reset Sequence
Beggining of the system
- Set pma_init and reset_pb signals in high.
- Check stability of INIT_CLK and GT_REFCLK
- Deassert pma_init followed by reset_pb
Normal operation
- Assert reset. Wait for a minimum time equal to 128*user_clk's time-period.
- Assert pma_init. Keep pma_init and reset asserted for at least one second to prevent
the transmission of CC characters and ensure that the remote agent detects a hot plug
event.
- Deassert pma_init.
- Deassert reset_pb.