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MIMD (Memory (Physical Organization (Centralized shared memory (Large…

- - - - Large caches
      - <100 processors
      - Same memory for all processors
        (1 memory, multiple banks)
      - HW or non cache coherent
    - - Supports large processor counts
      - Requires High-bandwidth interconnection
      - Each processor has its own memory
  - - - physical address unique only within a single processor
      - Processors communicate via send - receive primitives
      - Less HW, easier design
      - Easier control of data placement
        (no automatic caching)
      - More complex to program
        (explicit communication)
      - High message passing overhead
      - Requires reception techniques
        (interrupts / polling)
    - - any processor can reference any memory location
      - Unique physical address
      - Lower latency and low overhead in cache
      - Ease of programming
        (implicit communication with LOADS/STORES)
      - Easier HW controlled caching
      - Requires sync ops
      - Complex scalability
- - - - on write miss -> write-invalidate
      - on read miss -> write-update / broadcast
      - write-invalidate
        the address is invalidated in all other caches before actual writing
      - write update
        the writing processor streams the new data on the bus and all copies are updated
    - - True sharing misses
        happens because the line has been invalidated by a write from another processor
      - False sharing misses
        happens when a line is invalidated because another word in the line has been written into by another processor
  - - - Unique location that stores the sharing status
        (it can be physically distributed)
      - For each blocks records:
        
        its state (Shared, Modified, Uncached)
        
        which processor has a copy of it
        
        which processor is the owner (write)