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Structure and Function of the Processor (Components (Registers…
Structure and Function of the Processor
Components
ALU
performs arithmetic and logic operations on data
can perform instructions such as ADD, etc.
can perform shift operations (shifting bits within a register) and boolean operations (comparing two values and using AND/OR/NOT operators)
Control Unit
controls and coordinates activities of the CPU
directs the flow of data between the CPU and other devices
accepts an instruction
decodes the instruction into sequential steps
manages the instructions execution
stores resulting data back in memory or registers
collection of instructions it can carry is called an instruction set
Registers
Program Counter: holds the address of the next instruction
next instruction in sequence
where in a branchj to jump to, as specified by the CIR
Accumulator
takes place of general purpose registers
used to 'accumulate' the result of the currently running instructions
stores intermediate results of the current data processing
Memory Address Register: holds the address of the memory location from where the data is coming or where it's going to
Memory Data Register: temporarily stores data from memory before it is processed
Current Instruction Register: holds the current instruction
special memory cells that operate at very high speeds
place where ALU operations take place
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Busses
data
used to return locations to the CPU
signals can travel both ways
consists of 8, 16, 32 or 64 separate lines
provides instructions between system components
size
transmits data held in a word of memory between processor components and memory
largest operand that can be held in a word is related to size of data bus
wider data bus can transmit more bits per instruction or larger values
control
used to send control signals
signals can travel both ways
control lines must be provided so there isnt conflict between outgoing and incoming signals
bus request: indicates that a device is requesting the use of the data bus
bus grant: indicates CPU has granted access to data bus
memory write:sends data from the data bus to be written in the addressed location
memory read: places data from the addressed location on the data bus
Interrupt Request: indicates it when a device requests the CPU
Clock: used to synchronise operations
address
used to send an address when the CPU needs to access a particular memory location.
signals can only travel one way
divides up memory into 'words' (fixed size group of digits) which are handled as separate units by the processor and have their own specific addresses.
each word has its own specific address
width of address bus determines maximum possible memory capacity of the system.
transmits memory addresses of words that are used as operands so that data can be retrieved and sent back to the processor.
set of parallel wires connecting two or more components of a computer.
three busses collectively known as the system bus
each bus is a shared transmission medium
FDE Cycle
decode
instruction held in CIR is decoded
split into opcode and operand
opcode determines type of instruction and hardware used to execute it.
operand holds
address of data to be used - copied to MAR
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actual data to be operated on - copied to MDR
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data that should be passed to ALU or ACC
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execute
opcode is carried out on the operand
fetch
address for next instruction copied from program counter
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instruction copied to MDR and content of PC incremented to next instruction
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contents of MDR copied to CIR
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CPU Performance
clock speed
system clock generates series of signals
CPU cannot perform operations faster than the clock cycle
processor activities begin on a clock pulse
1 clock cycle per second = 1 Hetrz (Hz)
faster clock speed = instructions completed faster
number of cores
one core = one processor = one instruction carried out at a time
multicore = two or more linked processors in the same circuit
each core able to process a different instruction at the same time
twice the no of processors is NOT = twice the processing speed
some software not able to take advantage of the full processing power
cache
small amount of memory in the CPU
very fast, very expensive
instructions that are needed repeatedly copied into cache so they can be fetched faster
three levels of cache
first = smallest and fastest...
pipelining
allows next instruction to be fetched while the current one is still being processed
able to speed up operations as CPU spends less time idle
instruction pipeline
stages in which an instruction is moved through the processor
fetched, buffered and executed
arithmetic pipeline
represents parts of an arithmetic operation
can be brken down and overlapped as they are performed
common in microprocessors used in personal computers
can perform as many as 6 instructions simultaneously (Intel Pentium)
Architectures
Harvard
computer architecture with physically separate memories for instructions and data
can be faster than Von Neumann as data and addresses can be fetched at the same time
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parallel data and instructions may be used
used extensively with Digital Signal Processing(DSP) systems
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audio and speech signal processing
biomedical signal processing
seismic data processing
data image processing
two different memories can have different characteristics
in embedded systems, instructions can be held in ROM and data memory in R/W memory
larger word size used where more instruction memory than data memory is needed
instruction data bus can be wider than the data bus
also used in embedded systems
include special purpose computers which operate in real-time
programs tend to be large
Von Neumann
specifies components of a computer and processor where a shared memory and bus is used for both data and instructions
stored program concept
machine code instructions are fetched and executed serially by a processor that performs arithmetic and logic operations
a program must be resident in main memory to be executed
machine code instructions are fetched from the memory one at a time and decoded and executed in the processor
Von Neumann machine
same data bus used to transfer both data and instructions
single address bus used to transfer addresses of data and instructions
same word length used for all memory - for both data and instructions
data and programs share the same memory
used in conventional processors (e.g. PCs)
programs can be optimised in size
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contemporary
incorporate both architectures
e.g. one main memory for data and instructions but cache divided into instructions and data cache
