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VLIW (Structure (Multiple ops in one instruction (Fixed number of …
VLIW
Structure
Multiple ops in
one instruction
Fixed number of
instructions (4 -16)
Fixed number of instruction kind
(e.g. 2 L/S, 2 ALU, 2FP)
Different and specified
latency per instr. kind
Scheduled entirely by compiler
Multiple instr per cycle
The hardware requires
Parallelism within instruction
No RAW check
No data use before data ready
aka no data interlock
Loop Unrolling
Loop Iterations independent
of each others
Software pipeline
Each instruction can be thought
as an instant in a pipeline (see 09.21)
RRB
Rotating Register Base
Allocate new register
set for each loop
Add value to logical register
to get physical reg. number
Value to add is determined
by the latency of the inside instr.
CONS
Huge number of registers
to keep FUs active
Large Data Transfer
FUs <-> Register Files
High bandwidth bw
i-cache and IF stage
Large code size
PROS
Simple HW
Easy to increase #FU
Good compilers can exploit
parallelism at maximum
Very Long Instruction Word