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EE2024 (Programming for Computer Interfaces) (Part I (ARM Instruction Set…
EE2024 (Programming for Computer Interfaces)
Part II
Inter-Integrated Circuit (I2C) Protocol
Interrupt System & NVIC
Universal Asynchronous Receiver/Transmitter (UART) Protocol
Part I
Introduction to Microprocessor & ARM
Short History of Computing & ARM
ARM Cortex-M3 - NXP LPC1769
Speed: 120 MHz
100 pins
4 functions each pins
64 KB On Chip SRAM
32 KB SRAM on SoC
2 -16 KB SRAM blocks
In-built NVIC
512 KB Flash Memory
GPIO ports
Ethernet MAC
USB Interface
General Purpose DMA controller
2 SSP, SPI interface, 4 UARTs, 2 CAN channels
8 Channel 12-bit ADC, 10-bit DAC, motor control PWM
4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC
Module Overview
Microprocessor Concepts
2.1 Functional units
Input
Keyboard
Touchpad
Mouse
Camera
Output
Displays
Printers
Main Memory
Dynamic RAM (DRAM)
Static RAM (SRAM)
Processor
Arithmetic & Logic Unit (ALU)
Circuit for performing arithmetic & logic operations
Timing & Control Circuits
For fetching program instructions & data from memory
Registers
16 or 32 registers typically
Hold one word of operand data
In LPC1769, 1 word = 32 bits
Cache Memory
Adjunct to main memory
Smaller & faster than main memory
Holds sections of program & data currently being executed
Secondary Memory
Magnetic Disks
Optical Disks
Flash memory devices
2.2 Instruction & Programs
Instruction types
Load
Read a data operand from memory or input device into processor
Store
Write a data operand from a processor register to memory or output device
Operate
Perform arithmetic or logic operation on data operands in register
Example: C = A + B
Load R2, A
Load R3, B
Add, R4, R2, R3
Store R4, C
Instruction: specifies operation & location of its data operands
32-bits word holds 1 encoded instruction
Sequence of instructions executed sequentially
Program & data stored in main memory
2.3 Processor components
Program Counter (PC) Register
Holds memory address of current instruction
Instruction Register (IR)
Holds current Instruction
General Purpose Registers
Holds data & addresses
Timing & Control Circuits, Arithmetic & Logic Unit (ALU)
Fetch & execute instructions
Fetch cycle (for all instructions)
Send address in PC to memory circuits; issue READ
Load instruction from memory to IR
Increment PC to point to next instruction
Execute cycle (action depends on instruction)
Actual processing is done here
Example: Load R2, A
Send address A to memory circuits; Issue READ
Load contents of memory into register R2
2.4 Memory organization
Consists of millions of cells
1 cells hold a bit of information
0 or 1
Information handled in larger units
1 word
Group of n bits
Word length
16 to 64-bits
Memory
A collection of consecutive words of size specified by word length
Word & Byte Encoding
Common word length: 32-bits
Can store 32-bit SIGNED integer or 4 8-bytes
bit b32 is sign bit
Words in memory may store data or machine instruction for program
Each machine instruction mac require 1 or more consecutive words for encoding
Addresses for Memory Locations
Byte Addressibility
Byte size: 8-bits
Word length: 16 - 64-bits
Impractical to assign an address to each bit
Provide a byte-addressable memory
Assigns an address to each byte
Each memory loc. has distinct address
Number 0 to 2^k - 1 used as addresses for successive locations in memory
2^k locations constitute address space
Memory size set by k (number of address bits)
Examples: k = 20 -> 2^20 or 1M locations
Examples: k = 32 -> 2^32 or 4G locations
Memory Operations
Memory
Contains data & program instructions
Control circuits
Initiates transfer of data & instruction between memory & processor
Read operation
Memory retrieves contents @ address loc. given by processor
Write operation
Memory overwrites contents @ given loc. with given data
2.5 Instruction execution, branching,looping
Instruction must support the following
STORE & LOAD
OPERATE
Program sequencing & control
I/O transfers
RISC & CISC Instruction Sets
Reduced Instruction Set Computers (RISC)
1-word instructions
Require arithmetic / logic operands to be in registers
Simpler, faster, more power efficient, cheaper
Load/store architecture
Only instructions are used to access memory operands
Instructions/data stored in memory
Processor Register (PC) contents initially invalid
Addressing mode specifies memory location
Complex Instruction Set Computers (CISC)
Multi-word instructions
Allow operands directly from memory
Instruction Execution / Sequencing
2-phase procedure
fetch
#
execute
#
Branching & Looping
Conditional branch instruction
When a certain condition is true
Placing address containing required instruction into PC
Fetching & executing that instruction & subsequent
Loop
Operations that needs to be performed repeatedly
Implement by branching repeatedly to start of section of program until some terminating condition is satisfied
2.6 Condition codes
Can maintain information on results of arithmetic or logical instructions
Condition code flags (in status reg.)
N (negative)
1 if result negative
Z (zero)
1 if result zero
V (overflow)
1 if overflow occurs
C (carry)
1 if carry-out occurs
word=32-bits, half-word=16-bits, byte=8-bits
ARM Cortex-M3 Overview
3.1 Internal Architecture
32-bit Microprocessor
32-bit data path, 32-bit register bank, 32-bit memory interface
Harvard architecture
Separate instruction & data bus
Instruction & data accesses can take place simultaneously
Performance of processor increases
Data accesses do not affect instruction pipeline
Buses
Multilayer Advances Peripheral Bus (APB)
Provides separate bus for each APB master
Masters include CPU, General Purpose DMA controller, Ethernet MAC & USB interface
Provides communication with no arbitration delays
Split Advanced Peripheral Bus (APB)
Allows higher throughput with fewer stalls between CPU & DMA
Single level of write buffering
Allows CPU to continue without waiting for completion of APB writes
3.2 Registers
Registers R0 to R15
R0 to R12
32-bit General-purpose register
R0 to R7
Low registers
R8 to R12
High registers
2 Stack pointers (R13)
Banked: only 1 is visible at a time
Main Stack Pointer (MSP)
Default Stack Pointer
Used by kernel & exception handlers
Process Stack Pointer (PSP)
Used by application code
Lowest 2 bits of stack pointers always 0
Always word-aligned
Link Register (R14)
Storage of return address when subroutine is called
Program Counter (R15)
Current program address
Can be written to control program flow
Special Registers
Program Status Registers (PSR)
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR)
Can be accessed together or separately using special register access instructions; MSR & MRS
When accessed as a collective item, xPSR is used
read PSRs using MRS instruction
modify APSR using MSR instruction
EPSR and IPSR are read-only
Interrupt Mask Registers
PRIMASK
FAULTMASK
BASEPRI
Control Register (CONTROL)
ARM Instruction Set & Assembly Language
4.1 Introduction to ARMv7-M
ARM Instruction Set Characteristics
RISC-style aspects
All instruction at most 32-bits long
Only LOAD & STORE instructions access memory
Arithmetic & Logic instructions operate on processor register contents
CISC-style aspects
Auto increment (pre & post indexed) & PC-relative addressing modes provided
Condition codes used for conditional execution of instructions
Multiple word LOADS & STORE implemented with single instructions
Assembly Language: Basic Syntax
label:
opcode operand1, operand2, .. @ Comments
label
is optional
represents memory address
convenient for accessing an instruction in memory
branching & looping
subroutine calls
can also represent a defined value
accessing data item in memory
eg. as a variable
Calling an Assembler Function from C program
extern int asm_func(int x,int y);
Input parameters: R0, R1, R2, R3
Output parameter: R0
In assembly language prog (.s)
asm_func:...
Similar to subroutine
Ends with
BX LR
to return to C calling program
Branch Indirect (register): PC <- LR
4.2 Memory Addressing
Memory Allocation for Data
Data declarations
Constants
use .word assembler directive
eg.
NUM1: .word 123, 456
eg.
POINTER: .word NUM1+4
Static variables
use .lcomm assembler directive
eg.
.lcomm ANSWER 4
Labels
eg.
NUM1
,
POINTER
&
ANSWER
Load/Store with Immediate Offset
LDR instruction loads a register Rt with value from memory
STR instruction stores a value in register Rt to memory
Offset addressing
Assembly language format
LDR/STR Rt,[Rn {, #offset}]
Offset value is added to or subtracted from address obtained from register
Rn
Result is used as address for memory access
Value in register
Rn
is unaltered
PC-Relative Addressing
Only for LDR
Base register is the PC
LDR loads a register with value from a PC-relative memory address
Memory address is specified by a label or by an offset from the PC
4.3 ASMv7-M Foundation
Immediate Operands & Instr Suffixes
Immediate operands
#imm12
range 0 - 4095
12-bits
#imm8
range 0 - 255
8-bits
#imm8m
treat this like #imm8
#
8-bits
#imm16
range 0 - 65535
16-bits
Instruction suffix
for arithmetic & logical instructions
op{S}
eg.
ADDS R4, R2, R3
updates condition code flag
#
Operand2
Constant / Immediate
Specify constant in the form #constant
where constant must be <imm8m>
Register with optional shift
Specify register in the form: Rm {, shift}
where Rm is register holding the data for 2nd operand
shift is an optional shift to be applied to Rm
Condition Codes
Application Program Status Register (APSR) contains the following condition flags
#
Carry occurs if result of
an addition is greater than or equal to 2^32
a subtraction is positive or zero
an inline barrel shifter operation in a move or logical instruction
Overflow occurs when result of an add/subtract/compare is greater than or equal to 2^32 / less than -2^31
4.4 Basic ARMv7-M Instructions
Move Instructions
MOV
MOV Rd, Operand2
MOVW
MOVW Rd, #imm16
Arithmetic Instructions
ADD
ADD {Rd,} Rn, Operand2
ADD {Rd,} Rn, #imm12
ADDS updates the condition code flag
SUB
SUB {Rd,} Rn, Operand2
SUB {Rd,} Rn, #imm12
SUBS updates the condition code flag
MUL
MUL {Rd,} Rn, Rm
Multiply
MLA
MLA Rd, Rn, Rm, Ra
Rd: destination
(Rn * Rm) + Ra
32-bit result
Multiply with Accumulate
Compare Instruction
CMP
CMP Rn, Operand2
Performs Rn - Rm & update condition code flags N, Z, C, V
CMN
CMN Rn, Operand2
Performs Rn + Rm & update condition code flags but discard result
Compare Negative
4.5 Conditional Execution
Arithmetic, comparison/test & move (w suffix S) instructions cause condition code flags in the APSR to be set
#
Conditional execution of subsequent instructions can be obtained by using suffixes EQ, NE, LT, GT
in branch
within an IF-THEN (IT) instruction block
EQ - Equals
NE - Negative
LT - Less Than
GT - Greater Than
4.6 Branch Instructions
IF_THEN (IT) Block
IT
Only 1 conditional instruction
ITE
2 conditional instruction
ITET
3 conditional instruction
ITETT
4 conditional instruction
Conditional branch
Assembly language format
B{cond} label
Branches to location indicated by label if the condition code flags satisfy {cond}
PC <- label
Eg. BEQ LOCATION
branches to LOCATION if Z=1
4.7 More ARMv7-M Instructions
Logical Instructions
op
ORR
bit-wise logical OR
EOR
bit-wise logical XOR
BIC
bit clear; logical AND NOT
ORN
logical OR NOT
AND
Logical AND
Assembly Language format
op {Rd,} Rn, Operand2
Eg.
AND Rd, Rn, Rm
Test Instruction
TST
Test
Assembly language format
TST Rn, Rm or #value
Performs bit-wise logical AND of the 2 operands
TEQ
Test Equivalent
Assembly language format
TEQ Rn, RM or #value
Performs bit-wise logical Exclusive OR of the 2 operands
Updates condition code flags N & Z. C may be updated due to Operand 2.
Similar to ANDS & EORS but discards result.
Shift & Rotate Instructions
OP
LSL
Left Shift Left
LSR
Left Shift Right
ASR
Arithmetic Shift Right
ROR
Rotate Right
Assembly language format
OP Rd, Rm, Rs
OP Rd, Rm, #n
#n refers to number of bits to rotate
RRX Rd, Rm
Rotate Right with Extend
4.8 Advanced Memory Addressing
Immediate Offset with Index
Pre-indexed addressing
Assembly language format
LDR/STR Rt, [Rn], #offset
Offset value is added / subtracted from address obtained from Rn
Result is used as the address for memory access & written back into Rn
Post-indexed addressing
Assembly language format
LDR/STR Rt, [Rn, #offset]!
Address obtained from Rn is used as address for memory access
Offset value is added / subtracted from the address & written back into Rn
Load using Pseudo-Instructions
Instruction that is composed of simpler instructions
Eg.
LDR R3, =0xA123B456
LDR R3, MEMLOC
MEMLOC: .word 0xA123B456
Pseudo-instruction
Eg.
LDR R2, =NUM1
NUM1: .word 123
POINTER: .word NUM1
Multiple Word Load & Store
Any subset of processor register can be loaded or stored with Block Transfer instructions
LDM
STM
Eg.
LDMIA R10!, {R0, R1, R6, R7}
4.9 Stack & Subroutines
Stack
Full descending stack operation model
SP (R13) points to last data pushed into stack memory
When PUSH, SP decrements by multiple of 4 before new data is inserted
Subroutines
Subroutine linkage
BL SUBADDRESS
Branch with Link
Actions taken
Value of PC is stored in R14 (LR), the Link Register
LR <- PC
A branch is taken to SUBADDRESS
Embedded System Development through C Programming (CMSIS)
5.1 CMSIS Components
Cortex Microcontroller Software Interface Standard (CMSIS)
Specified by ARM
CMSIS defines for a Cortex-M Microcontroller System
Register names of core peripherals & names of core exception vectors
Common way to access peripheral registers & common way to define exception vectors
User can reuse template code easily
CMSIS is intended to enable combination of software components from multiple middleware vendors
5.2 C Libraries & Programs
CMSIS
Lib_CMSISv1p30_LPC17xx
core_cm3.h/c
ARM Cortex-M3 specific
LPC17xx.h
LPC17xx series specific
system_LPC17xx.h/c
LPC17xx series specific
Lib_MCU
Contains functions to access & control peripherals on Cortex-M3 & LPC1769
PINSEL
GPIO
NVIC
UART
I2C
Lib_EaBaseBoard
Contains functions to access & control peripherals & devices on the EA Baseboard
Pin Connect Block
6.1 Introduction
Allows most pins of the microcontroller to have more than 1 potential function
Configuration registers control the multiplexers to allow connection between the pin & on chip peripherals
Peripherals should be connected to appropriate pins prior to being activated & prior to any related interrupts being enabled
Activity of any enabled peripheral function that is not mapped to related pin should be considered undefined
Selection of single function on a port pin excludes other peripheral functions available on the same pin.
GPIO input stays connected & may be read by software or used to contribute to the GPIO interrupt feature
6.2 Pin Function select register (PINSEL)
Example
PINSEL_CFG_TYPE PinCfg;
PinCfg.Funcnum = 0;
Here is where the pin function select register is configured
Function available: 00, 01, 10, 11
PinCfg.Pinnum = 22;
PinCfg.Portnum = 0;
General Purpose Input/Output (GPIO)
Part I
7.2 Overview of GPIO in LPC1769
5 GPIO ports of 32 pins
Not all pins are in use
Accelerated GPIO functions
GPIO registers located on a peripheral AHB bus for fast I/O timing
Mask registers allow treating set of port bits as a group
All GPIO registers are byte, half-word and word addressable
Entire port value can be written in 1 instruction
Direction control of individual port bits
All I/Os default to input with pull-up after reset
7.4 GPIO Registers
GPIO Registers for digital IO function
FIOxDIR (x = 0 to 4)
Fast GPIO Port Direction Registers
Each bit controls each pin's direction
Can access (R/W) by
Word (32-bits): FIOxDIR
Half-word (16-bits): lower - FIOxDIRL, upper - FIOxDIRU
Byte (8-bits): FIOxDIR0 (bits 0-7) to FIOxDIR3 (bits 24-31)
Default value: 0
FIOxSET (x = 0 to 4)
Fast GPIO Port Output Set Registers
Used when GPIO is in OUTPUT mode
Each bit of FIOxSET is used to produce a HIGH level output at the corresponding GPIO pin
Writing 1 produces HIGH level at the pin
Writing 0 has no effect
If any pin configured as input or other function, writing 1 to corresponding bit in FIOxSET has no effect
Writing/reading is conditioned by FIOxMASK bits
Writing/reading sets/returns the contents of the FIOxSET register
Can access (R/W) by
Word (32-bits): FIOxSET
Half-word (16-bits): lower - FIOxSETL, upper - FIOxSETU
Byte (8-bits): FIOxSET0 (bits 0-7) to FIOxSET3 (bits 24-31)
Default value: 0
FIOxCLR (x = 0 to 4)
Fast GPIO Port Output Clear Registers
Used when GPIO is in OUTPUT mode
Each bit of FIOxCLR is used to produce a LOW level output at corresponding GPIO pins
Writing 1 produces LOW level at pin & clears corresponding bit set earlier using FIOxSET
Writing 0 has no effect
If any pin is configured as input or other function, writing 1 to corresponding bit in FIOxCLR has no effect
Writing is conditioned by FIOxMASK bits
Can access (Write Only)
Word (32-bits): FIOxCLR
Half-word (16-bits): lower - FIOxCLRL, upper - FIOxCLRU
Byte (8-bits): FIOxCLR0 (bits 0-7) to FIOxCLR3 (bits 24-31)
Default value: 0
FIOxPIN (x = 0 to 4)
Fast GPIO Port Pin Value Registers
Reading Each bit provides state / logic level of corresponding pin
where pin is configured to perform ONLY digital functions
regardless of whether pin is configured for input / output / GPIO / alternate digital function
If pin has an analog function, value read in FIOxPIN is not value
Writing to FIOxPIN register stores the value in port output register, bypassing the need to use both FIOxSET & FIOxCLR registers
Writing / reading is conditioned by FIOxMASK bits
Can access (R/W) by
Word (32-bits): FIOxPIN
Half-word (16-bits): lower - FIOxPINL, upper - FIOxPINU
Byte (8-bits): FIOxPIN0 (bits 0-7) to FIOxPIN3 (bits 24-31)
Default value: 0
FIOxMASK (x = 0 to 4)
Fast GPIO Port Mask Registers
Affects read/write access of FIOxPIN, FIOxSET & FIOxCLR
A 0 in this register's bit enables read/write to corresponding pin
If a bit in this register is 1
corresponding pin will not be changed with write access
if read, will not be reflected in updated FIOxPIN
Can access (R/W) by
Word (32-bits): FIOxMASK
Half-word (16-bits): lower - FIOxMASKL, upper - FIOxMASKU
Byte (8-bits): FIOxMASK0 (bits 0-7) to FIOxMASK3 (bits 24-31)
GPIO Interrupt Registers
GPIO Overall Interrupt Status Register
GPIO Interrupt Enable
GPIO Interrupt Status
GPIO Interrupt Clear Register
7.5 GPIO supporting functions in MCU library
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t GPIO_ReadValue(uint8_t portNum);
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
uint32_t FIO_ReadValue(uint8_t portNum);
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
7.1 Overview of GPIO
Behaviour can be controlled/programmed through software
Pins have no special purpose and is unused by default
Idea for GPIO
Chips might need additional digital control lines in future
Designers have to arrange additional circuitry to provide them
Having GPIOs available from the chip can save hassle
Capabilities
direction
pins can be configured to be input or output
enable mask (GPIO mask)
pins can be enabled / disabled
input values are readable
typically high = 1, low = 0
output values are writable / readable
Generic pin on chip
Part II
7.1 GPIO Pins as Interrupt Source
Port 0 & 2 can provide a single interrupt for any combination of port pins
Each port pin can be programmed to generate an interrupt on rising/falling edge or both
Edge detection is asynchronous, so may operate when clocks are not present
Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts & overall pending GPIO interrupts
GPIO0 & GPIO2 interrupts share the same position in NVIC with
External Interrupt 3
7.2 GPIO Interrupt Registers
GPIO Overall Interrupt Status Register: IOIntStatus
Indicates presence of interrupt pending on all of GPIO interrupt ports
read-only
1 status bit per port
GPIO Interrupt Enable
For port 0/2 Rising/Falling Edge
IO0IntEnR
IO0IntEnF
IO2IntEnR
IO2IntEnR
Each bit enables the rising/falling edge interrupt for corresponding port 0/2 pin
read-write
GPIO Interrupt Status
For port 0/2 Rising/Falling Edge
IO0IntStatR
IO0IntStatF
IO2IntStatR
IO2IntStatF
Each bit indicates the rising/falling edge interrupt status for port 0/2
read-only
GPIO Interrupt Clear Register
For port 0/2
IO0IntClr
IO2IntClr
Writing 1 into a bit in this register clears any interrupts for corresponding port 0/2 pin
Write-only
Steps for configuring & using GPIO Interrupts
Decide whether interrupt is rising / falling edge
Configure GPIO interrupt
Enable specific interrupt in GPIO Interrupt Enable register
When GPIO interrupt occurs, EINT3 will be triggered & its interrupt handler will execute
Determine the specific GPIO interrupt that has occurred by checking the GPIO Interrupt Status Register
Do processing (short)
GPIO Interrupt Clear the specific GPIO Interrupt
Exit from EINT3 interrupt handler