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SoC Modeling (4. Modeling Terms (programmer view accurate (timing may be…

- - - - when accurate, the model is called PV + T
- - - - approximately timed
        
        cycle accurate
        
        most accurate in timing and order
        
        maximum simulation time
        
        most details
        
        least abstract models
- - - - Therefore the timing of the TLM 2.0 model will be loose or approximate
  - - - However TLM can still be used to define designs in a less abstract, more detailed way
  - - - provides two guidelines for coding styles that define how loosely timed and approximately timed blocks are written
        
        loosely timed models have just enough timing information to run operating systems and handle multicore systems, allowed to run ahead of the master simulation clock, allowed to bypass the transaction based block to block interface entirely and have direct access to areas of memory within a target function, again to accelerate simulation
        
        approximately timed models add just enough timing information to make the model useful for architectural exploration and performance analysis. The model run in lock step with the master simulation clock
    - - four use-cases
        
        software development
        
        software performance estimation
        
        architectural analysis and performance modeling
        
        hardware verification
    - - mechanisms which are C++ application programming interfaces (APIs) that ensure interoperability
        
        blocking / non-blocking interfaces
        
        direct memory interfaces
        
        sockets
        
        generic payload
        
        phases
        
        interoperability is achieved by defining transactions using a core interface between a socket on the initiator of a transaction and a socket on its target.
        
        The data passing over the resultant link is carried in the generic payload format, which defines standard slots for the kinds of information that get passed around in memory mapped systems.
        
        The handshaking involved to send and acknowledge receipt of the payload is carried using a base protocol, which defines a set of phases marking the beginning and end of a request and a response
- - - - does not own separate thread, automatically activated, cannot call code that calls wait()
    - - own a separate thread, automatically activated, can call code that call wait()
    - - own a separate thread, automatically activated, can call code that call wait() with certain conditions
  - - - processes communicate with each other through signals or channels
        
        read()
        
        write()
        
        sc_signal<data_type>variable_name;
    - - ports of a module are its interface that interacts with the external world and pass information to and from a module and trigger actions within a module
        
        sc_in<port_type>_name
        
        sc_out<port_type>_name
        
        sc_inout<port_type>_name
    - - sc_clock variable_name(name, period, duty_cycle, start_time, positive_first, time_unit );
    - - facilitates communication functionality between two modules
        
        sc_fifo<data_type>_name(buffer_size)
  - - - write test bench as a set of .cpp and .h files
        
        write top level design instantiating DUT and test bench
        
        simulate design
  - - - native C++ data types
        
        sc_in<length>
        
        sc_bv<length> bitwise operation
        
        sc_logic<length> to model X and Z
        
        sc_bigint<length> for arbitrary arithmetic operations
        
        slowest