Memory system design in SoC (2. Architecture (Von neumann (benefits…
Memory system design in SoC
bus and storage for data and instruction
the ratio of memory allocated to instruction and data is determined by hardware. Once the chip is made, it cannot be changed.
embed data within the code
it is often
to be able to
write to the instruction memory
i.e set software break points in memory
high speed execution time is at the cost of
more hardware complexity
two or more internal buses which allow
to both instructions and data
time for execution
of program is
single common memory space
where both program instructions and data are stored
more flexible, since modern computers are design to perform wide variety of tasks
single data bus
which fetches data and instructions
taken by the cpu to fetch a program is
I and D caches with a common address space
what architecture benefit more from cache memory?
two memory array
use of neighboring data
reuse of specific data
to reduce memory access latency
3. Types of on-chip memory
Static Ram (SRAM)
lower cost per bit
slower than SRAM
retain data even if there a break in power supply
5. Processor to processor communication
read and write
cannot be executed concurrently
each processor has its own local ram
another processor can use the
common bus to send data over
to another processor local memory, and the
receiving processor can access concurrently
. Effective cut down traffic by half
Shared dual port ram
uses the same local ram
processor to processor
alternative of using ram, a
but processors must be
aware of who's writing and reading
6. Two type of performance perspective
performance of memory system
across all instruction and data references
performance of memory system
across critical code regions
where will processor execute its initialization code from?
is data loaded from remote memories?
is application code small enough to fit in the processor local on-chip instruction ram or is a cache necessary?
how will the processor load application data?
is on-chip local data ram big enough to satisfy run time requirements for heap and stack?
is data pushed into the processor's local data ram by an outside agent like DMA?
does the processor directly load data as input or as load instructions?
how does output data get to other parts of SoC?
can all data fit entirely into processor's local data ram?
7. Deciding memory system in SoC
that needs more than
real or virtual memory with off die portions of memory,
may need L2 cache
, large memory requirement
virtual memory with DRAM, L2 cache on die
that fits in less than
SRAM, no virtual table, L1 cache only
How much memory can we put on die?
need to consider access time, write time, addressability
How to tune the memory system?
use simulation to obtain informations
number of execution
total instruction committed
data write instructions executed
cache misses, cycle per instruction
1. Why does memory occupy most of the die space?
A lot of silicon is dedicated to memory because of
memory hungry applications