Please enable JavaScript.
Coggle requires JavaScript to display documents.
Programmable System on Chip (P-SoC) (Contains (Computing Components (Power…
Programmable System on Chip (P-SoC)
Define: An integrated circuit that incorporates all components of a computer or other electronic systems
Basic idea: To
combine programmable logic and processor on the same die
with additional peripherals
Reduce
cost
A
single chip
embedded system platform
Enables easy integration of methods
to ensure security of architecture
Contains
Computing Components
Microprocessor/Microcontroller
Signal processing blocks
Graphics processing unit
Clock management blocks
Power and thermal management blocks
PL powered off
Allow PS to operate while PL is powered off or on a different voltage for low power design
Cortex A9 Processor Standby Mode
Clock gating
Disable clock to subsystems, switching activity stops
Programmable voltage for I/O banks
DDR3 & LPDDR2
Memory device operate in low power mode
Signal acquisition
Programmable logic
Look up table
Flip flops
Communication Components
Communication interfaces
External memory interfaces
Storage Components
On chip memory
Interconnect Components
Bus based or Network on chip based
Based on Advanced Microprocessor Bus Architecture (AMBA) interconnect protocol
I2C
Controller Area Network (CAN)
Universal Asynchronous Receiver Transmitter (UART)
Gigabit Ethernet (GigE)
Direct Memory Access (DMA)
Extended Memory Interface (EMIO)
Programmable logic
Programmable
Define: programming of hardware blocks and interconnect
Basic h/w block includes: memory, DSP blocks, on-chip storage
Interconnect means: configurable interconnect architecture
Difference between programmable and configuring?
Programmable has unbound possibilities
Configuring has limited choices
Processing System (PS)
Control
handles interaction of peripherals
example: interfacing with memory
Programmable Logic (PL)
Connectivity
Define: Connecting different existing or new modules together
AXI
Master
Initiates the transaction
Slaves
Responds to the initiated transaction
AXI Interconnect
Handles connection between masters and slaves
Contain address decoding table to resolve master communication target
Translate data width according to slaves requirements
Hierarchical
Used up all available ports
To segregate the designs
Important to note that address of slaves must not overlap and must follow address alignment rule
A standard to allow units to communicate
Easy to maintain, update and debug
Units can be reuse in other designs
Encoder blocks
Image processing blocks
Why is there many different designs of devices?
Because different market segment require different specification & computing power
The main difference is on the PL side only
Security
Why important?
Processor can execute unauthorized application code and compromise the system
Solution: Secure Boot Process
Boots up only
encrypted
and
authenticated PS image
and
PL bitstream
Use Cases
Access peripheral configuration registers
Static video stream
Access data path configuration registers and memory
Interactive image processing
Low latency/high bandwidth shared work spaces, moves data between SW and HW domains
Motor control
PL configuration path
JTAG
PCAP
how is it different from ICAP?
ICAP
Allows
partial reconfiguration
or
reconfiguration of PL
initiated by logic in PL