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High Level Synthesis (3 main constructs in C/C++ (Important things to take…

- - - - Recursive functions
      - Dynamic memory allocation
      - Pointers that cannot be determined during compilation
    - - HLS tool support limited pointer arithetic
      - Limited support for pointer casting
      - Limited support for pointer array
      - HW design is bit accurate
        
        What are the benefits of using properly sized variables/signals/buses?
        
        Arbitrary precision datatypes is used to describe bit accurate design
        
        Int#W, uint#W
        
        ap_int< #W >, ap_uint< #W >
        
        ap_fixed< WL, FL >, ap_ufixed< WL, FL >
- - - - No unrolling
        
        One loop iteration is executed in one clock cycle
      - Partial unrolling by factor K
        
        Loop body copied K times, K bodies get executed in one clock cycle
        
        Requires K port ram & K operators
      - Complete loop unrolling
        
        Entire loop body is executed in one clock cycle
        
        Requires MAX port ram & MAX operators
    - - Loops that have the same enter and exit conditions can be merge together
        
        Because large number of loops can leads to complex FSM with many control signals and also lead to longer latency
    - - For more than one consecutive loops, each loop will be executed after the previous loop has finished execution.
        
        By applying loop pipelining, could make them execute in parallel
    - - Break a loop with unknown exit conditions into two loops, one loop with determinate exit condition, the other will unknown exit condition
        
        The determinate exit condition loop can then be optimized
    - - If there are no conflicting data dependencies, a loop can be pipelined so that its next iteration begins earlier than the default value
  - - - Even though memory blocks have limited read/write ports, the throughput can be improved by mapping a large array to multiple memory block
        
        Block
        
        original array is split into equally sized block of consecutive elements
        
        Cyclic
        
        original array is split into equally sized blocks interleaving the elements
        
        Complete
        
        original array is split up into individual registers for each array location
        
        flexible to access all elements at the same time
    - - Combines array partitioning with vertical mapping
        
        Increase in bit width for each single read, resulting in wide read, thus fewer read/write access
        
        less switching, less power dissipation
    - - Two instance of array will be mapped to two individual BRAMs
        
        Leads to waste of BRAMs if the size of the array is smaller
        
        Horizontal Mapping
        
        Merging two array into a new 1D array
        
        What is the drawback of this approach?
        
        Parallel memory access is reduced to sequential memory access
        
        Vertical Mapping
        
        An array with higher bit width is created by combining two smaller array
        
        What are the benefits and drawback of this approach?
        
        maintain parallel access
        
        Explicitly manage the MSBs treated as zeros if the two smaller array does not have same length
        
        Between horizontal and vertical mapping which one would put more pressure on the address bus when accessing the memory?
        
        Which one would result in more power dissipated in accessing the bus?
    - - implemented as a FIFO
        
        does not require address
        
        consistently provide data to consecutive loops or functions to prevent unnecessary bottleneck due to external address generation and control circuitry
        
        Overheads such as keep track of new write address and previous read address
  - - - Fully utilize hardware resource to achieve parallelism
    - - To force the tool to use same operator by pipelining
    - - Packs the members of a struct into a single wide word to reduce the control overhead in access them
  - - - Suppose function A is called multiple times within another function B, the hardware implementation of A can be reuse
        
        However, if function A is called by other functions C, D and E, the hardware implementation of A will not be reusable for different function as function A is in different hierarchy
    - - Define: convert a sequential function call hierarchy to a parallel
      - Important to note that one function must produce some data to be consume by another function
    - - Define: To maintain function hierarchy while remove or simplify control logic
        
        By replacing a condition with a function
        
        Thus, allow each function to be optimized
    - - Define: replacing the function with the body code that made up of
    - - Define: Pipeline function to increase throughput
- - - - A system model is created using blocks, simulated and tested and RTL description automatically generated
    - - A system is described at a high level of abstraction in C or C++ or systemC. It is simulated and test and RTL description automatically generated
      - does not need to manually design the system using verilog or vhdl
      - Designer just need to focus on algorithm refinement
      - Goal: Allow hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation.
        
        designers develops the module functionality and the interconnect protocol
        
        HLS tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations
- - - - Physical synthesis (place and route)
- - - - Formal Model
        
        Allocation
        
        RTL Microarchitecture
        
        Contains a data path controlled by a finite state machine (FSM).
        
        FSM models the control flow which the data flow and related operations are implemented in the data path
        
        Allocation of function units from the FU library
        
        Scheduling
        
        Scheduling of different operations under a given timing constraint
        
        Involves assigning operations to different clock cycles
        
        Relevant to SoC designers
        
        Hardware binding
        
        Refers to binding operation to functional units under area constraint
        
        Aim is to minimize the number of resources used
        
        Resource Sharing
        
        Understand one resource sharing algorithm
        
        Refer to High Level Synthesis Note pg 11 - 14
        
        Relevant to SoC designers
        
        FU library
        
        Functional units (area, delay, power)
        
        Intermediate representation (IR) of a C-program
        
        Control and Data flow graph
        
        Shows the control flow and data dependencies
      - Works with an intermediate representation that a compiler uses while compiling
- - - - Step 3: apply suitable optimizations and re synthesize and implement
        
        Step 4: repeat step 2 and 3 until design meets the requirements
      - Observe which operations took more than one cycle
      - observe the resources assigned to different operations
      - observe which operations were scheduled in the same control step
- - - - Thus, leads to early design closure
      - Writing own-self will lead to unforeseen error
      - Save time
- - - - header file
        
        global variables, #defines, function declaration, data_types
        
        test bench file