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Programmable Logic (1.1 Define: A set of resources for reconfigurable…

- - - - Improve performance and fabrication margin as compared with PLA because only one portion is programmable, thus less potential of error
      - Simpler to manufacture
      - Less expensive
      - Less flexible
      - Faster
  - - - Flexible
      - Efficient logic
      - Expensive
  - - - Used for padding data with bits
    - - Connects Logic blocks (PLA)
      - Low power consumption
- - - - Configurable Logic Blocks (CLBs)
        
        Interconnect track
        
        Horizontal and vertical interconnects
        
        Switch Box
        
        Intersection of interconnect tracks
        
        Connection Box
        
        Input / output connection between CLBs
      - Delay locked loops
      - Block ram
      - Interconnect resources
      - I/O blocks
      - Even without CPU, it is still a programmable system because we can implement a soft core processor instead
- - - - improve the skew characteristic of clocks
    - - generate more clocks by dividing / multiplying the input clock
    - - shift the phase of clocks to generate a phase-shifted clock
    - - Forward an input clock to an output port of your SoC directly
    - - generate different frequency by setting certain parameters, for example O0, O1 etc
- - - - PCAP
      - ICAP
  - - - Achieve same throughput at lower clock frequency
        
        Thus, lower power consumption
    - - Thus, lower power consumption
  - - - Multiple computation paths in resource rich FPGA
      - Same performance at lower clock frequencies
      - Stream data flow
    - - Pipeline
        
        Abundance of registers
      - Register re-timing
      - Programmable interconnects
        
        Option to run different design at different frequencies
  - - - Triple Mode Redundancy (TMR)
      - Voting function
  - - - R = T(sw) / T(hw)
    - - Identify hot spots using code profiling
      - Data flow consideration
        
        Aim to keep the accelerator fed with data at all times or as quickly as possible
        
        DMA
      - Lots of computations
      - Function or tasks that can be parallelized
    - - I/O rate limit capped
      - Resource limits
        
        Limited DSP blocks
      - Processor
        
        if the processor has to create data to the accelerator, this will create additional latency before the accelerator starts execution