Issues in SoC Design (Power (Multiple clock domains (VDD (Unified Power…
Issues in SoC Design
Big die suffers more from
Smaller die lead to silicon
Yield = e ^ (pA)
p = Defect density
company invests more technical and financial efforts in reducing defect density
A = Die area
Principle of Marginal Utility
Die area, A = 25mm ^ sq
Design = 18mm ^ sq
I/O port = 3mm ^ sq
Computation optimization = 4mm ^ sq
what is it?
what is the issue for performance?
Why worry about power usage?
Battery operated system
Multiple voltage island
Multiple clock domains
Unified Power Format
Common Power Format
Why reliability is of concern?
of the product should correspond to its
Why do faults occurs?
Defects probability increases along with die area
Operating at high frequency lead to
and increase in noise sensitvity
How to deals with faults?
Design for testability
Build in Self Test structures
Memory and function scrubbing
Check for faulty areas
in memory, faulty functional units is
no more used
during application execution
what is the issue for configuration?
Why large design space exist?
Many components to choose from
Multiple implementation options available for components
on/off chip memory
with more advance technology, size of node becomes smaller and smaller
Power and reliability constraints
the amount of energy could draw varies with different power source available on the device
required to allocate additional space for cooling device
prevent component from overheating that could result in permanent damage or temporary malfunction
different performance goals