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CompOrg: MIPS (5 STAGES (Output of each stage is stored into shadow…
CompOrg: MIPS
5 STAGES
Instruction Fetch
Instruction Decode
Execute
Memory Access
Output of each stage is stored into shadow register
Stage 6 moves values in shadow reg to next stage
Write Back
Data Structures
Instruction Memory
Decode Instruction
.RT
.RD
shamt
.func
immediate
jump
pc + 4
.opcode
.RS
RegFile
#
Data Memory
Logic Operations
MUX
ALU
Functions: Determined by .func part of instruction
OR
ADD
AND
Set on less than
NOR
outputs
Zero output controls beq instruction (take branch or PC+4)
ALU result
Control Unit
MIPS C Project
Header Files
regFile.h
Source Files
Main.c
regFile.c
Development Process
5 stages
main memory
block mode fills and write buffer
I - Cache
D - Cache
Execution Types
Single Cycle
Pipeline
dynamic branch prediction
Instructions
R - Type
add
sub
I - Type
LW
SW