VHDL
Simulation Model
Behavioural level
RTL Level
Logic Level
Corners
Best Case (Low temp, High voltage)
Worst Case (High Temp, Low voltage)
Typical Case (Normal temp, Nominal voltage)
Statement
Concurrent
sequential
Language Style
Object Oriented
Key code
Entity
Architecture
entity entA is
port (a: In std_logic
b: out std_logic);
architecture arcA of entA is
signal sigA: std_logic;
begin
end;
comment
"--"
/ comment /
Instantiation
U1: entA port map (a => a
b=>b);
click to edit
Data Type
Std_logic
Std_ulogic
Boolean
Array
time
array
character
integer