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Main Memory (Logical vs physical address space (Paging system (the mapping…
Main Memory
Logical vs physical address space
Logical address generated by CPU for a program
logical address = (page number, page offset)
Physical address - address seen by memory unit (RAM)
Same in compile/load time, different in execution time
Paging system
the mapping of logical memory of a program to physical memory using a
page table
implementation of paging system
using
page table base registe
r (PTBR) and
page table length register
(PTLR)
all data/instructions requires 2 memory accesses, one for page table, one for data/instruction
optimized using
translation look-aside buffer (TLB)
using
address space identifiers
Effective access time (EAT)
EAT = p(MA+e) + 1-p(2MA+e)
Memory Protection - using valid-invalid bit in page table on PTLR
sharing - shared code and private code
structures
Hierarchical paging
forward mapped PT
inverted page tabe
hashed page tables
segmentation system
protection is easier than aging system since segments are same type
fragmentation less in paging than segmentation system because no external fragmentation with pages
Address binding
compile time - if memory locations are known
load time - generate relocatable code if memory locations not known at compile time
Execution time - binding delayed until run-time if process can be moved during its execution
needs hardware for address maps, base and limit register