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COMPUTER FUNCTION AND INTERCONNECTION (DATA BUS (Data lines that provide a…
COMPUTER FUNCTION AND INTERCONNECTION
Computer Components
based on concepts developed by John von Neumann
Referred to as the von Neumann architecture
Data and instructions are stored in a single read-write memory
The contents of this memory are addressable by location, without regard to the type of data contained there
Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next
Hardware and Software Approaches
Software
contains code and instruction
MAJOR COMPONENT
CPU
Instruction interpreter
Module of general-purpose arithmetic and logic functions
I/O Components
Input module
Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system
Output module
Means of reporting results
Instruction Cycle
EXECUTE CYCLE
• Interpret & Perform
—Processor-memory
– data transfer between CPU and main memory
—Processor-I/O
– Data transfer between CPU and I/O module
—Data processing
– Some arithmetic or logical operation on data
—Control
– Alteration of sequence of operations
– e.g. jump
—Combination of above
Instruction Cycle State Diagram With Interrupts
Multiple interrupts can occur concurrently
• Two approaches
—Sequential processing
– Processor will ignore further interrupts while processing one
interrupt
– Interrupts remain pending and are checked after first
interrupt has been processed
– Interrupts handled in sequence as they occur
—Nested processing
– Low priority interrupts can be interrupted by higher priority
interrupts
– When higher priority interrupt has been processed,
processor returns to previous interrupt
DATA BUS
Data lines that provide a path for moving data among system modules
The number of lines determines how many bits can be transferred at a time
Bus Interconnection Scheme
ADDRESS BUS
Used to designate the source or destination of the data on the data bus
CONTROL BUS
Used to control the access and the use of the data and address lines
Quick Path Interconnect
Multiple direct connections
Direct pairwise connections to other components eliminating the need for arbitration found in shared transmission systems
Layered protocol architecture
These processor level interconnects use a layered protocol architecture rather than the simple use of control signals found in shared bus arrangements
Packetized data transfer
Data are sent as a sequence of packets each of which includes control headers and error control codes
