Please enable JavaScript.
Coggle requires JavaScript to display documents.
Evaluating FPGA-based Architectures in Early Design Phases (FPGA as HwAcc,…
Evaluating FPGA-based Architectures in Early Design Phases
Methodology
aoc (intel)
OpenCL
reports
fmax
HW resources
HLS files
System-level Simulation
Architecture
Blocks
Applications
Task-graph
SAVE
FPGA as HWAcc
'# PRR
HW - Board Interface
HW_HWTASK
Power
Static
(standby,idle)
Periphery (transceivers, I/O)
PRRs
Board interface (BI)
Dynamic
Periphery (transceivers, I/O)
Core Logic
quartus
power
periphery
core
ModelSim
Performance (Latency) Model
Power Model
OpenCL
Polybench
Task-Graph
Applications
high-level language
Host + Kernel
FPGA as HwAcc
DPR - Dynamic and Partial Reconfiguration
PRR - Partially Reconfigurable Region
(each region as a HwAcc)
PRM - Partial Reconfiguration Modules
Reconfiguration Time (Throughput)
Bitstream (full and partial)
Resource Utilization, Internal Fragmentation
(Morales-Vilanueva, ...)
Reconfiguration Power (Bonamy et al.)
DPR
(Vipin, Fahmy)
logic density, reduced configuration time, adaptive HW systems
reduced configuration time
PR (Partial Reconfiguration) - not in parallel
fewer PRR:
better optimization (area), larger reconfiguration time
More Modules per region, larger # reconfigurations
PR - Intel Quartus UG
Wrapper logic for PR regions when the PR regions do not have identical top-level interfaces
Paper's Structure
Introduction
Work's Contributions
FPGA PE in SAVE
Methodology's Steps description
Background
OpenCL
FPGA HLS (aoc intel)
Methodology
Flow and tools
aoc (intel)
quartus
SAVE Simulator
System-level Simulation
FPGA implementation as a Virtual Hardware Accelerator(s)
Structure, System, TLM (implementation)
Architectural Blocks
Workload Application
Modeling the Workload
Performance (Latency) Model
Power Model
Case Study
Polybench Apps
"Little Apps"
2DCONV, 3DCONV, 3MM, ATAX,BICG, GEMM, GESUMMV, MVT
"Big Apps"
2MM, GRAMSCHM, SYR2K, SYRK, CORR, COVAR, FDTD-2D
Architecture
A15
Mali T628
Arria10GX
' #PRR
Results and Discussion
Conclusions and Future Work
Related Works
simhaccel
System-level sIMulator for Heterogeneous Architectures with fpga-enabled virtual harware aCCELerators
S
IM
H
A
CCEL