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Architectural Synthesis (What? (Input (Constraints (Timing: Latency, Area:…
Architectural Synthesis
What?
Input
Behavioral Description
Constraints
Timing: Latency
Area: Resources
Output
Circuit :
How?
Primary Operations
Scheduling
Binding
Convert Description to
Data-Flow Graph
Scheduling
Which cycle does each operation happen in?
Motivation: minimise the latency
Assume that each operator takes a clock cycle. Define operators in such a way
Algorithms
ASAP
Assume Infinite Resources
Start an op'n whenever its predecessors are ready
Finds Latency Bound
ALAP
Solves a latency-constrained Problem
Latency Bound = ASAP Latency Bound
List Scheduling
Representations
Bound Sequencing Graphs
DFG + Resource Binding
Scheduled Sequencing Graphs
DFG + Start-time Annotation
Binding
Which instance of an operator's resource does each operation
Motiviation: minimise the resources
Steering Logic
Control and Connections