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Digital Logic Design and Analysis (DLDA) (Combinational Logic Design…
Digital Logic Design and Analysis (DLDA)
Number Systems and Codes
Binary Number System
Binary Arithmetic
Addition
Subtraction
Multiplication
Division
Octal Number System
Octal Arithmetic
Addition & Subtraction
7‟s and 8‟s complement method
Decimal Number System
Hexadecimal Number System
Hexadecimal Arithmetic
Addition & Subtraction
15‟s and 16‟s complement method
Codes
Gray Code
BCD Code
Excess-3 Code
ASCII Code
Error Detection and Correction
Hamming codes
Combinational Logic Design
Encoders Priority encoder
Decoders
One bit
Two bit
Demultiplexer tree
4-bit Magnitude Comparator
Demultiplexer
Multiplexer tree
Multiplexer
one digit BCD Adder
4 bit adder subtractor
Look Ahead Carry Adder
Four Bit Ripple adder
Half Subtractor Full Subtractor
Half and Full Adder
ALU IC 74181
Sequential Logic Design
Introduction
State Diagrams
State table
State machines
concept of Moore and Mealy machine
Flip-flop conversion
Timing Diagram
Master Slave J-K Flip Flops
Race around condition
Truth Tables and Excitation Tables of all types
Concepts of Flip Flops
J-K
T
D
SR
SR latch
Counters
UP- DOWN counter
Shift Registers
PIPO
SIPO
PISO Bidirectional Shift Register
SISO
Universal Shift Register
Modulus of the Counters
Ring and twisted ring/Johnson Counter
Design of Asynchronous and Synchronous Counters
Sequence Generator
Introduction to VHDL
Architecture
Modeling Styles
Entity
Concurrent and sequential statements
Fundamental building blocks Library
simple design examples for combinational circuits and sequential circuits
Boolean Algebra and Logic Gates
Canonical forms
Standard SOP and POS form
Boolean function reduction using Boolean laws
Boolean functions
Theorems and Properties of Boolean Algebra
Basic Digital gates
Positive and Negative Logic
K-map Method
2- Variable
3-Variable
4- Variable
Don‟t Care Condition
Quine-McClusky Method
NAND-NOR Realization
Digital Logic Families
Power Consumption
Fan in and Fan out
Terminologies like Propagation Delay
current and voltage parameters
noise margin
with respect to TTL and CMOS Logic and their comparison